A Hardware Solution for the HEVC Fractional Motion Estimation Interpolation

Nowadays many devices can handle with digital videos, especially with high definition, even for portable devices, as smartphones and tablets. However, high definition videos demand a high amount of information to be represented. The current video coding standards use a set of new techniques to increase its coding efficiency. One of these techniques, used by H.264 and HEVC (High Efficiency Video Coding), is the Fractional Motion Estimation (FME). One of the main steps of the FME is the interpolation step, which is responsible for the generation of the fractional positions. This paper presents a hardware design focusing on the interpolation step of the FME for the emerging HEVC standard. The designed architecture was described in VHDL and synthesized for Altera Stratix III FPGA. The architecture is able to generate the fractional samples for videos with QFHD (3840 x 2160 pixels) resolution in real time at 48 frames per second. Keywords— FME, Fractional Motion Estimation, FME HEVC, Interpolation HEVC, FME Interpolation